HPCC Glossary (2.1) Index Page

HPCC Glossary

This is a glossary of terms on High Performance Computing and Communications and is essentially a roadmap or information integration system for HPCC technology. A typical entry is laid out like this:

architecture (n.) The basic plan along which a computer has been constructed. Popular parallel architectures include processor arrays, bus-based multiprocessors (with caches of various sizes and structures) and disjoint memory multicomputers. See also Flynn's taxonomy.

where cross-references are hyperlinks to other entries, or in some cases to other documents on the net. Some entries like that for BLAS software point to the software source itself, available on the net from sites like the National HPCC Software Exchange.

Here are accelerators to alphabetic sections of the glossary:

The construction of this glossary is of necessity an ongoing process in an active field like HPCC, and so entries will be updated and augmented periodically. Watch for the version numbers. The master copy is stored at NPAC.

Several people have contributed to this glossary, especially Jack Dongarra, Geoffrey Fox, Joseph Meister and Greg Wilson and many of our colleagues at Edinburgh and Syracuse. Any further contributed entries, suggested revisions, or general comments are welcome.

Ken Hawick, hawick@npac.syr.edu

M. A. Saleh Elmohamed, saleh@npac.syr.edu