Shared Memory Architecture

Main Feature: All processors can directly access all memory locations in the system, thus providing a convenient mechanism for processors to communicate.
Convenient in the sense of:
- location transparency
- abstraction supported is the same as that on today's uniprocessors.
Memory usually is centrally placed.
Symmetric multiprocessor (SMP) systems use this centralized memory approach, where each processor is connected to a shared bus. This shared bus handles all accesses to main memory and I/O.
A schematic view of the centralized shared memory model in an SMP system is given below. Each processor (denoted by P) accesses memory through a shared bus and has a local cache (denoted by $).
- As we will see later, the presence of local caches introduces interesting problems of cache coherency in shared memory environments.
Example machines supporting this type of architecture: (NOTE: some of these machines are also classified as PVPs or Parallel Vector Processors)
This architecture belongs to the MIMD model.
A schematic view of a typical memory model for shared memory parallel programs is shown below.

Collection of processes have a common region of physical addresses mapped into their virtual address space, in addition to the private region, which contains the stack and private data.