Basic HTML version of Foils prepared 19 September 1997

Foil 58 Supercomputer Architectures in Years 2005-2010 -- I

From Master Set of Foils for 1997 Session of CPS615 CPS615 Basic Simulation Track for Computational Science -- Fall Semester 97. by Geoffrey C. Fox
1 Conventional (Distributed Shared Memory) Silcon
  • Clock Speed 1GHz
  • 4 eight way parallel Complex RISC nodes per chip
  • 4000 Processing chips gives over 100 tera(fl)ops
  • 8000 2 Gigabyte DRAM gives 16 Terabytes Memory
2 Note Memory per Flop is much less than one to one
3 Natural scaling says time steps decrease at same rate as spatial intervals and so memory needed goes like (FLOPS in Gigaflops)**.75
  • If One Gigaflop requires One Gigabyte of memory (Or is it one Teraflop that needs one Terabyte?)
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