Basic HTML version of Foils prepared 19 September 1997

Foil 61 Performance Per Transistor

From Master Set of Foils for 1997 Session of CPS615 CPS615 Basic Simulation Track for Computational Science -- Fall Semester 97. by Geoffrey C. Fox


1 Performance data from uP vendors
2 Transistor count excludes on-chip caches
3 Performance normalized by clock rate
4 Conclusion: Simplest is best! (250K Transistor CPU)
5 Millions of Transistors (CPU)
6 Millions of Transistors (CPU)
7 Normalized SPECINTS
8 Normalized SPECFLTS

in Table To:


© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Feb 22 1998