Basic HTML version of Foils prepared 17 November 1998

Foil 78 SGI Origin III

From Master Foilset for HPC Achitecture Overview CPS615 Basic Simulation Track for Computational Science -- Fall Semester 98. by Geoffrey C. Fox
NPAC Summary of Origin 2000 Architecture
1 The SysAD (system address and data) bus of the previous figure connecting the two processors has a
  • peak bandwidth of 780 MB/s.
  • The same also for the Hub's connection to memory.
  • Memory bandwidth for data is about 670 MB/s.
2 The Hub's connections to the off-board net router chip and Xbow I/O interface are 1.56 GB/s each.
in Table To:

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