Basic HTML version of Foils prepared 17 November 1998

Foil 131 Tera Multithreaded Supercomputer

From Master Foilset for HPC Achitecture Overview CPS615 Basic Simulation Track for Computational Science -- Fall Semester 98. by Geoffrey C. Fox
Tera Architecture and System Links for Foil 79
This uses a clever idea developed over many years by Burton Smith who originally used it in the Denelcor system which was one of the first MIMD machines over 15 years ago
MTA(multithreaded architectures) are designed to hide the different access times of memory and CPU cycle time.
  • We used caches in conventional architectures
  • MTA uses a strategy that is typically used with coarser grain functional parallelism -- namely it switches to another task while current one is waiting for memory
  • Burtom emphasizes that hiding memory latency always implicitly requires parallelism equal to ratio of memory access to CPU operation speed

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