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A Short Overview of HPCC -- From GigaFlops to PetaFlops and From Tightly Coupled MPP's to the World Wide Web

Given by Geoffrey C Fox at CRPC Retooling Project Cornell on 7 May 1996. Foils prepared 7 May 1996

See SCCS-736 for overview of Parallel and SCCS 750 for distributed computing
We discuss current and near future architectures as well the yet different trends expected 10 years from now
COTS (see SCCS 758 and 732 for Web Software) philosophy dominates both hardware and software as success demands that niche applications leverage bigger fields
Latency Tolerance will be an essential feature of future algorithm and software
Data Parallelism is essential for success on large machines but current compilers are struggling
Coordination or Integration software is thriving


This mixed presentation uses parts of the following base foilsets which can also be looked at on their own!
Master Foils for A Short Overview of HPCC -- From GigaFlops to PetaFlops and From Tightly Coupled MPP's to the World Wide Web
Master Set B of Overview Material on Parallel Computing for CPS615 Foils
Master Foilset for HPCS95 Keynote Presentation
InfoVISION: Information Video Simulation Imagery ON demand
MetaComputing -- the Informal Supercomputer -- MRA Meeting Part I:Concepts and Issues
Master Set A of Overview Material on Parallel Computing for CPS615 Foils
Some Numerical Memory and MicroProcessor Projections for PetaFlops
Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing
Part B:Overview of Programming Paradigms and Relation to Applications
Part A:Overview of Programming Paradigms and Relation to Applications
Collection of GIF Images for General NPAC Projects 1995-March96

Table of Contents for A Short Overview of HPCC -- From GigaFlops to PetaFlops and From Tightly Coupled MPP's to the World Wide Web

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1 A Short Overview of HPCC
From GigaFlops to PetaFlops
From Tightly Coupled MPP's to the World Wide Web
2 Abstract of a Short Overview of HPCC
3 Performance of High End Machines Years 1940-2000
4 Peak Supercomputer Performance
5 Superficial Observations on High Performance Computing-II
6 Superficial Observations on High Performance Communication
7 However we need more than fast enough machines
We also need a large enough market to sustain technology (systems and software)
8 Some Important Trends -- COTS is King!
9 NII Compute & Communications Capability in Year 2000 --> 2005
10 Ultimate Vision and Implementation of NII and InfoVision
11 Comments on COTS for Hardware
12 Network Performance (1955 - 2005)
13 Growing Logic Chip Density
14 Technology Projections
15 Conventional Microprocessor Unit Performance Path
16 Primary Memory Chip Cost
17 Notes on Primary Memory $
18 Performance Per Transistor
19 Supercomputer Architectures in Years 2005-2010 -- I
20 National Roadmap for Semiconductor Technology --1992
21 CMOS Technology and Parallel Processor Chip Projections
22 Clock Speed and I/O Speed in megabytes/sec per pin through year 2013
23 Chip Density Projections to year 2013
24 Supercomputer Architectures in Years 2005-2010 -- II
25 Supercomputer Architectures in Years 2005-2010 -- III
26 Category III Petaflop Design -- Processor in Memory (PIM)
27 SIA-Based PIM Chip Projections
28 Petaflop PIM System Size
29 Comparison of Supercomputer Architectures
30 Bodega Bay Petaflops Applications Characteristics
31 Algorithm and Software Challenges -- The Latency Agenda!
32 Returning to Today - I
33 Returning to Today - II
34 Software Issues/Choices - I
35 General Applicability of HPF, HPF++, HPC++
36 The Sad Story of HPF and Some Applications
37 Software Issues/Choices - II
38 The Mapping of Heterogeneous Metaproblems onto Heterogeneous Metacomputer Systems
39 General VRML Example I
40 Software Issues/Choices - III

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