Basic HTML version of Foils prepared 24 August 98

Foil 24 Shared Memory MIMD Multiprocessor

From Master Foilset for CPS615 Introduction -- Material from Culler and Koelbel Computational Science for Simulations -- Fall Semester 1998. by Geoffrey C. Fox, Nancy McCracken
1 Processors access shared memory via bus
2 Low latency, high bandwidth
3 Bus contention limits scalability
4 Search for scalability introduces locality
  • Cache (a form of local memory)
  • Multistage architectures (some memory closer)
5 Examples: Cray T90, SGI Power Challenge, Sun
in Table To:

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