Parallel Computer Memory Structure

• For both parallel and sequential computers, cost is accessing remote memories with some form of “communication”

• Data locality addresses in both cases

• Differences are quantitative size of effect and what is done by user and what automatically

Processor

Cache

L2 Cache

L3 Cache

Main

Memory

Processor

Cache

L2 Cache

Processor

Cache

L2 Cache

Board Level Interconnection Networks

….

….

System Level Interconnection Network

L3 Cache

Main

Memory

L3 Cache

Main

Memory

Slow

Very Slow

Previous slide

Next slide

Back to first slide

View graphic version