HELP! * GREY=local LOCAL HTML version of Foils prepared July 2,1995

Foil 40 Rapid Prototyping Facility

From NPAC Centric view of Federal HPCC Program Trip to China(Beijing,Harbin) by Don Leskiw -- June23-July 5,1995. by Don Leskiw * Critical Information in IMAGE
A wafer containing multiple PIM (Processor-in-Memory) chips, each with 128kb of memory and 64 processors. 0.25M of these processors with memory have passed initial testing in a single Cray-3 quadrant as part of the Cray-3/SSS (Super Scalable System), a joint venture between NSA and Cray Computer Corporation.

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Tue Feb 18 1997