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\begin{document}

\title{A Comprehensive Taxonomy and System Architecture for ATM
Host-Network Interfaces}  

\author{Bo-kyun Na}

\organization{Dept. of Electrical Engineering and Computer Science \\
              Syracuse university}

\date{May 12, 2000}

\titlepage

%\slidecontents

%\sectioncontents

%\begin{slide}
%{\bf }
%\rule[0.1in]{8in}{0.02in}
% 
%\end{slide}

\begin{slide}
{\bf Current Network Systems}
\rule[0.1in]{8in}{0.02in}
\vfill
The current networks are:
\begin{itemize}
\item Service dependent: Telephony, computer neworks
\item Inflexibile: In adapting changes or new service requirements
\item Inefficient: Resource sharing between networks (Packet switching)
\end{itemize}
\vfill
The single service-independent network is:
\begin{itemize}
\item Flexible and future-safe in bandwidth (Adaptive network)
\item Efficient in the use of available resources (Statistical switching)
\item Less expensive (Single network $<$- manufacturing, operating,
maintaining) 
\end{itemize}
\vfill
\end{slide}

\begin{slide}
{\bf Review of Host-Network Interface Systems}
\rule[0.1in]{8in}{0.02in}
\vfill
Definition: A network I/O to connect host to network.
\vfill
With TCP/IP suites,
\vfill
\centerline{\psfig{figure=figures/generalHNI.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Problems of Current HNI Systems}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Poor protocol implementations: 
	\begin{itemize}
	\item Complicated and slow transport protocol
	\end{itemize}
\item Poor interface between applications and HNI: 
	\begin{itemize}
	\item Unnecessary data copying
	\item Low-speed system bus compared to CPU bus
	\end{itemize}
\item High overhead with OS functions and context switchings: 
\begin{itemize}
\item Process scheduling
\item Entities managements - timers, buffers, and connection states
\item Interprocess communication between application and
protocol-implementing processes 
\item Interrupts
\item Context switching
\end{itemize}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Conventional Classifications of HNIs}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item By the number of data copies made
\item By the processing capability of HNI's
\item By the memory access
\item By the host access
\end{itemize}
\vfill
\end{slide}

\begin{slide}
{\bf The Number of Copies in Data Transfer I}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Peter A. Steenkiste $et\ al$.
\item According to the system buffer, Host-network interfaces are
classified as:  
\begin{enumerate}
\item Traditional 5-access data flow,
\item Outboard buffering, 
\item DMA based host-network interface architectures.
\end{enumerate}
\item  Similarly, C. Dalton $et\ al$ analyzes TCP/IP protocol
implementation in terms of minimizing data movement in memory
(Afterburner HNI). 
\end{itemize}
\end{slide}

\begin{slide}
{\bf The Number of Copies in Data Transfer II}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter3/figures/SteenkisteTaxonomy.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Limitations of Current Taxonomies}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Comparative power 
	\begin{itemize}
	\item 	Only one category and non-hierarchical 
	\end{itemize}
\item predictive power 
	\begin{itemize}
	\item No inference of similarities or differences 
	\end{itemize}
\item Comprehensive power
	\begin{itemize}
	\item Authorization only the related architectures
	\item LAN, WAN, MAN, tightly-coupled or loosely-coupled systems
	\end{itemize}
\item Systematic power 
	\begin{itemize}
	\item No integration of the hardware and software features
	functional units 
	\end{itemize}
\end{itemize}
\end{slide}

%foil 8
\begin{slide}
{\bf Research Objectives and Approaches}
\rule[0.1in]{8in}{0.02in}
\vfill
HNI taxonomy is motivated and directed to:
\begin{itemize}
\item Construct an architectural knowledge base as a foundation (Descriptive)
\item Understand the position of architectures relative to one another
(Comparative or hierarchical)
\item Predict new designs that are optimized to service requirements
(Predictive I)
\item Precise System Model supporting Quantitative Performance Estimates
(Predictive II) 
\item Understand the relations between architectural components and
protocol processing functional units (Systematic)
\item Accordingly, construct a comprehensive atlas of HNIs within the
unified framework of the taxonomy (Comprehensive)    
\end{itemize}
\vfill
\end{slide}

\begin{slide}
{\bf Skillicorn's Taxonomy of Computer Systems}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item Three reasons for classifying architectures: 
	\begin{itemize}
	\item To understand what has already been achieved
	\item To reveal possible configurations to suggest other possibilities 
	\item To allow useful performance models to be built and used
	\end{itemize}
\vfill
\item More descriptive classification of the computer architectures
\item Extends Flynn's taxonomy in the multiprocessor category
\item A two-level hierarchy
	\begin{itemize}
	\item Upper level classifies computer architectures based on
	the numbers of processors for data and for instructions and
	the interconnections between them: $n$IP - $n$IM, $n$DP -
	$n$DM, IPs - DPs, and DPs - DPs 
	\item Lower level to distinguish variants even more precisely
	and based on the state machine level of processors
	\end{itemize}
\end{itemize}
\vfill
\end{slide}

\begin{slide}
{\bf System Model}
\rule[0.1in]{8in}{0.02in}

Two-context taxonomy, as the approaches:
\begin{itemize}
\item Architectural context: The HNI architectures and their limitations  
	\begin{itemize}
	\item Main components required to transfer data between host
	and network  
	\begin{itemize}
	\item Host CPU
	\item Main memory
	\item Cache memory
	\item Protocol processor or controller
	\item Network buffer
	\item Switch
	\end{itemize}
	\item Connections and the interactions between these components 
	\item PMS notation to simplify the block diagram of HNIs
	\item A system as an interconnected set of components or individual
	 devices associated with a set of operations.  
	\end{itemize}
\vfill
\item Protocol context: The implementation of network protocol functions 
	\begin{itemize}
	\item Identifying all the software functions, required to transfer 
	data (descriptive power)
	\item Mapping the software functions into the components identified
	at the architectural classification (systematic power)
	\item Identifying all possible techniques to develop a HNI
	(predictive power) 
	\item Protocol functional units:
	\begin{itemize}
	\item Routing/switching	
	\item Data copying
	\item Flow control
	\item Error handling
	\item Packetization/Depacketization
	\end{itemize}
	\end{itemize}
\end{itemize}
\vfill
\end{slide}

\begin{slide}
{\bf Performance Model}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item Rearranging protocol functional units so that it takes less time
(parallelization of protocol implementations) 
\item Reducing unnecessary data copying in main memory
	\begin{itemize}
	\item No data copying to system communication buffer in kernel space
	\end{itemize}
\item Fast host interfacing (low-speed system bus v.s. high-speed CPU bus)
	\begin{itemize}
	\item Increase the speed of system bus
	\item Through other medium (host register, dual-ported memory)
	\end{itemize}
\item Hardware implementation of protocol functional units 
	\begin{itemize} 
	\item On-board protocol processor
	\item CRC checking or Flow control
	\end{itemize}
\item HNI implements protocol functional units
	\begin{itemize}
	\item Avoiding system calls by OS and context switching
	\end{itemize}
\end{itemize}
\vfill
\end{slide}

\begin{slide}
{\bf Illustrative Example: Jaguar}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item University of California at Berkeley
\item Providing Java applications with efficient access to system resources
\item Retaining the protection of the Java environment
\item Allowing Java applications to directly manipulate memory outside
of the Java heap such as communication buffer
\item  JaguarVIA, as a Java interface to the Berkeley VIA
communication layer
\item Implemented with Intel PentiumII, Linux OS, and Myrinet network
interface board
\item Shown performance improvement only by optimizing API
\end{itemize}
\end{slide}

\begin{slide}
{\bf Continue...}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter3/figures/L1-JaguarVIA.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Continue...}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter3/figures/L2-JaguarVIA.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Syntactic Notation of Conventional HNIs}
\rule[0.1in]{8in}{0.02in}
This table shows our syntax notation for host-network
interface designs that have been reported in the literature.
\vfill
\centerline{\psfig{figure=figures/syntax-table.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Design of Intelligent HNI}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Highest performance 
\item Reducing the heavy loads of the host
 \begin{itemize}
 \item on protocol processing
 \item on system peripheral bus
 \end{itemize}
\item Support host to take more-processing required jobs
\end{itemize}
\end{slide}

\begin{slide}
{\bf Design Requirements}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item In architectural context,
 \begin{itemize}
  \item Protocol processing in HNI
  \item A better connection component than a system peripheral bus
  \item CRC checking by hardware component while data being transferred
 \end{itemize}
\item In protocol-implementation context,
 \begin{itemize}
  \item Implementation  in a pipelined or parallelized way
  \item Routing - source's and destination's addresses
  \item Data copying - direct transfer between $M_H$ to network FIFO
  \item Error handling - high speed CRC check for cell header and payload
  \item Flow control - on-board protocol processor counts cells
  \item Packetization - Fixed sized cell by $P_N$ -  message as a
  local data in host 
 \end{itemize}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Taxonomy-based Design Approach}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item In architectural context,
\begin{itemize}
\item $P_H - M_N$ : Burst transfer by cache controller ($B_{cc}$) for
 status and control information, start address and length of data, and
 connection establishment parameters. 
\item $M_C - M_N$ : $B_{cc}$ for data transfer.
\end{itemize}
\item In protocol-implementation context,
\begin{itemize}
\item The protocol processor packetizes in the fixed size.	
\item Virtual circuit switching (ATM).
\item User space memory - network FIFO data copying scheme.   
\item CRC-8 and CRC-32 by hardware, sequence number, MID, length
indicator of data.  FEC + ARQ for error correction.
\item Rate-based flow control.
\end{itemize}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Diagram for architectural context of intelligent HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter4/figures/L1-intellyHNI.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Diagram for protocol context of intelligent HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter4/figures/L2-intellyHNI.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Formal Performance Metrics: 1}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter5/figures/host-adaptor_connect.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Formal Performance Metrics: 2}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item $T_{\mu p}$: Clock cycle time of CPU data bus in nanoseconds. 
For Alpha 21164, it is $33 MHz$ or $30.3 nsec$.  
\item $T_{\mu c}$: Clock cycle time of adaptor control
processor. MC88110 has 25 nsec data bus clock cycle time for 64 bits. 
\item $L^f_{\mu p}$: The number of clock cycles per load from cache to
host CPU, or from network buffer to host CPU.
\item $L^f_{\mu c}$: The number of clock cycles per load from network
buffer to network-adaptor control processor. It takes 3-1-1-1 data
transfer clock cycles. 
\item $L^s_{\mu p}$: The number of clock cycles per load from main memory
to host CPU. For typical EDO (Expanded Data Output) dynamic RAMs,
7-2-2-2 data transfer clock cycles in a pipelined-burst mode.
\item $L^s_{\mu c}$: The number of clock cycles per load through
bus. It is supposed to have the same value with $L^s_{\mu p}$.  
\item $S^f_{\mu p}$: The number of clock cycles per store to the network
buffer, or to the cache from the host CPU.
\item $S^f_{\mu c}$: The number of clock cycles per store to one cell
FIFO in network 
adaptor.
\item $S^s_{\mu c}$: The number of clock cycles per store to main memory
from host CPU or to cell FIFO from main memory in conventional
architecture.  
\end{itemize}
\end{slide}

\begin{slide}
{\bf Transmitting Performance of Intelligent HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item For 48 Bytes data:
\item 3 slow loads ($M_H$ - 128 bits/load) in 7-2-2 $\mu P$ cycle
\item 3 fast stores (128 bits/store) in 5 clock cycles (3-1-1) to $M_N$  
\item 6 fast loads (64 bits) in 8 (3-1-1-1-1-1) clock cycles in
pipelined burst
\item 7 fast stores (64 bits) in 9 (8 payloads and 1 header) clock cycles 
\item 5 arithmetics and 1 branch instructions 
\end{itemize}

\begin{eqnarray*}
Throughput & = & \frac{48\ byte/cell \times 8\ bit/byte}{(3 L^s_{\mu p} +
3 S^f_{\mu P}) T_{\mu P} + (6 L^f_{\mu C} + 7 S^f_{\mu C} +
6\ computation) T_{\mu C}} \\  
 & = & \mbox{} \frac{384}{(11 + 5) (30.3 \times 10^{-9}) + (8 + 9 + 6)
(25 \times 10^{-9})}  \\  
 & = & \mbox{}   362.33 Mbps
\end{eqnarray*}

\vfill
\end{slide}

\begin{slide}
{\bf Transmitting Performance of Conventional OSIRIS HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item $P_N$ loads control information first, then loads and stores
directly cell payload into cell FIFO  
\item 1 slow load and store for control information 
\item 6 slow loads for data transfer in 7-2-2-2-7-2 clock cycles with
64-bit wide 
\item 7 fast stores - 6 for data and 1 for header 
\item 5 arithmetic and 1 branch instructions
\end{itemize}

\begin{eqnarray*}
Throughput & = & \frac{48\ byte/cell \times 8\ bit/byte}{(L^s_{\mu p}+
S^s_{\mu p}) T_{\mu p} + (6 L^s_{\mu c} + 7 S^f_{\mu C} + 6
computation) T_{\mu C}} \\   
 & = & \mbox{} \frac{384}{(7 + 7) (30.3 \times 10^{-9}) + (22 + 9 + 6)
(25 \times 10^{-9})} \\   
 & = &  \mbox{}  284.61 Mbps
\end{eqnarray*}
\vfill
\end{slide}

\begin{slide}
{\bf Segmentation Performance of intelligent HNI: worst case}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter5/figures/segthruput-cache.ps,width=4.5in,height=4.5in,angle=0}}
\vfill
\end{slide}

\begin{slide}
{\bf Segmentation Performance of intelligent HNI: best case}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter5/figures/segthruput-best.ps,width=4.5in,height=4.5in,angle=0}}
\vfill
\end{slide}

\begin{slide}
{\bf Receiving Performance of intelligent HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item In intelligent HNI for 48 Bytes: 
\item 6 fast loads (3-1-1-1-1-1) 
\item 6 fast stores (3-1-1-1-1-1)
\item 8 arithmetic and 4 branch instructions 
\end{itemize}

\begin{eqnarray*}
Throughput & = & \frac{48 Bytes}{( 6 L^f_{\mu c} +  6 S^f_{\mu c} +
12\ computation) T_{uC}} \\
   & = & \mbox{} \frac{384}{(8 + 8 + 12) 25 \times 10^{-9} } \\
   & = & 548.57\ Mbps
\end{eqnarray*}

\vfill
\end{slide}

\begin{slide}
{\bf Receiving Performance of OSIRIS HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item In OSIRIS for 48 Bytes:
\item 6 fast loads and stores to $M_N$
\item 8 arithmetic and 4 branch instructions
\item 6 slow loads of DMA data transfers (64 bit/load) 
\item 3 fast stores in main memory (128 bits/store)
\item 6 fast store to $M_N$ can be ignored by the dual-ported memory
feature 
\end{itemize}

\begin{eqnarray*}
Throughput & = & \frac{48 Bytes}{3S^f_{\mu p} \times T_{\mu
p} + ( 6 L^s_{\mu c} +  6 S^f_{\mu c} + 12\ comp) T_{uC}} \\
    & = & \mbox{} \frac{384}{ 5 \times 30.3 \times 10^{-9} + (22 + 8 + 
12) 25 \times 10^{-9}} \\
   & = & 319.60\ Mbps    
\end{eqnarray*}

\vfill
\end{slide}

\begin{slide}
{\bf Reassembly Performance of intelligent HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter5/figures/reasmthruput-cache.ps,width=4.5in,height=4.5in,angle=0}}
\vfill
\end{slide}

\begin{slide}
{\bf Answer to Research Questions}
\rule[0.1in]{8in}{0.02in}

\begin{itemize}
\item What are the problems in designing an HNI?
  \begin{itemize}
  \item Complicated and slow transport protocol implementations
  \item Interfacing between applications and a network system, 
  \item High overhead caused by OS functions and context switchings 
  \end{itemize} 
Instead of solving these problems directly, we researched the use of a 
comprehensive
taxonomy for better analyzing and understanding of problems of
  HNI's as well as for designing of new improved HNI systems   

\item What are the characteristics of current taxonomies?
\begin{itemize}
\item Designed to support only the argument about superiority of the
  proposed solution
\item Only one category supports only a narrow breadth of comparison
\item Resulting in lack of predictive, comprehensive powers
\item Thus, we proposed a comprehensive taxonomy for HNIs
\item Two context layers
 \begin{itemize} 
	\item Architectural and protocol-processing contexts
	\item Each context has several taxons forming a hierarchical structure. 
 \end{itemize}
\end{itemize}

\item How does our proposed taxonomy help one to design an HNI?
\begin{itemize}
\item Network environment should be analyzed and understood to get the
	minimum and maximum requirements of the intended HNI
\item Using the explanatory and predictive features of our taxonomy, the design
requirements can be compared with other systems and can be summarized
\item Optimized components in architectural and
protocol-implementation contexts can be selected from the descriptive 
features
\item  Thus, the category of the required design can be known and the
performance of the design can be inferred from the system model
implied by our taxonomy.
\end{itemize}

\item Therefore, major problems of host-network interfaces can be addressed
by our taxonomy. This is the contribution of my thesis for HNI systems. 

\end{itemize}
\vfill
\end{slide}

\begin{slide}
{\bf Future Research}
\rule[0.1in]{8in}{0.02in}
\vfill
\begin{itemize}
\item Extension of protocol-implementation context to include API 
\item The overhead of OS affects API implementations and causes the
whole communication network environment to slow down, even though the
HNI has low latency and the host runs applications with high computing
power.  
\item Thus, the API should be treated as one important functional unit
in protocol-implementation context of the taxonomic system to analyze
more accurately HNIs. 
\item One example - JaguarVIA 
	\begin{itemize}
	\item a Java API to improve performance of communication and
	I/O methods in Java programming. 
	\end{itemize}
\end{itemize}
\vfill
\end{slide}


%%%%%%%%%%%%%%%%%%%% background foils %%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\begin{slide}
{\bf Skillicorn's Taxonomy}
\rule[0.1in]{8in}{0.02in}
\vfill
Using his taxonomic scheme, Skillicorn established a single category
of 28 classes:
\vfill
{\large
\begin{tabular}{|c|c|c|c|c|c|c|l|} \hline 
class & $n$IP & $n$DP & IP-DP & IP-IM & DP-DM & DP-DP  & Name \\
 \hline \hline 
3 & 0 & $n$ & - & - & $n-n$ & $n\times n$ & loosely coupled dataflow \\
4 & 0 & $n$ & - & - & $n \times n$ & - & tightly coupled dataflow \\
6 & 1 & $n$ & $1-1$ & $1-1$ & $1-1$ & - & von Neumann uniprocessor \\
8 & 1 & $n$ & $1-n$ & $1-1$ & $n-n$ & $n \times n$ & type 1 array
 processor \\
9 & 1 & $n$ & $1-n$ & $1-1$ & $n\times n$ & - & type 2 array processor
 \\
13 & $n$ & $n$ & $n-n$ & $n-n$ & $n-n$ & - & separate von Neumann
 uniprocessors \\
14 & $n$ & $n$ & $n-n$& $n-n$& $n-n$ & $n\times n$ & loosely coupled
 von Neumann \\
15 & $n$ & $n$ & $n-n$& $n-n$& $n-n$ & - & tightly coupled von Neumann
\\ \hline 
\end{tabular}
}
\vfill
\end{slide}

\begin{slide}
{\bf The Processing Capability of HNI's}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item E. Cooper and $et\ al$,
\item Due to the difference in performance and implementation
complexity,
\begin{itemize}
\item Protocol processor on board
\item Memory accessing way (user and kernel spaces in main memory)
\item DMA capability
\end{itemize}
\item Simple HNIs
 	\begin{itemize}
	\item Host as protocol processor
	\item Memory accessing on both of user and kernel spaces
	\end{itemize}
\item Intelligent HNIs
	\begin{itemize}
	\item On-board protocol processor
	\item Memory accessing only on user space
	\item DMA capability
	\end{itemize}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Memory Access}
\rule[0.1in]{8in}{0.02in}
According to the address-mapping spaces and data accessing mechanisms,
David Banks and $et\ al$ classifies HNIs as mapping: 
\begin{itemize}
\item In memory space
\item In I/O space
\begin{itemize}
\item Programmed I/O
\item Direct Memory Access (DMA)
\item Burst mode transfer by memory controller
\end{itemize}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Host Access}
\rule[0.1in]{8in}{0.02in}

D. Henry and C. Joerg proposes four categories:
\begin{itemize}
\item OS-level DMA based
\item User-level memory mapped
\item User-level register mapped
\item Hardwired
\end{itemize}
\end{slide}

\begin{slide}
{\bf Architectural Context}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item The characteristics are from the logical structures and
 connections of hosts, host-network interfaces, and a network. 
\item Principal components are:
	\begin{itemize}
	\item Host CPU
	\item Main memory
	\item Cache memory
	\item Protocol processor or controller
	\item Network buffer
	\item Switch
	\end{itemize}
\item By PMS (processor-memory-switch) notations:
	 \begin{itemize}
	 \item The relations between processor, memory, and I/O devices. 
	 \item A system as an interconnected set of components or individual
	 devices, associated with a set of operations.  
	 \end{itemize}
\end{itemize}
\end{slide}

\begin{slide}
{\bf continue...}
\rule[0.1in]{8in}{0.02in}
 \begin{itemize}
 \item Host CPU unit is to execute instructions of the user
 application which may require a communication to, if required, the
protocol processor related to the communication, and to transform data
usually in ways that correspond to basic arithmetic operations.  
 \item Main memory unit is an intelligent storage device that passes
data to and from the host CPU. 
 \item Cache unit consists of a small fast memory that acts as a buffer
between the main memory and the host CPU.
 \item Network buffer unit is a staging and speed-matching area for
data in transit between the host and the network. It consists of a
network buffer memory and network FIFOs. Network buffer memory is the
storage for transport-layer data (so called message) and information
related to the control and management parameters, while network FIFOs
are two set of registers for sending and receiving. It also provides
the protocol processor with contention-free memory access to the
packet data. 
 \item Protocol processor unit manages packet processing and various
bookkeeping functions associated the protocol.
 \item Switch unit provides connectivity between other functional
units in one way of programmed I/O, DMA (Direct Memory Access), burst
transfer by memory controller, or register accessing.  
\end{itemize}
\end{slide}

\begin{slide}
{\bf Protocol-Implementation Context}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Packetization/Depacketization
\item Data copying
\item Flow control
\item Error handling
\item Routing/switching
\end{itemize}
\end{slide}

\begin{slide}
{\bf Packetization/Depacketization}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Data is bundled and transmitted as packets of bit streams with
some overhead bits to avoid network errors    
\item A message larger than the packet data size
\item OS or a protocol processing unit fragments the message into a
series of packet data
\item Reassembles the packets into the message in the receiving process.
\item Classified by who processes and by packet length as following: 
\begin{enumerate}
\item A variable-sized data unit that is packetized by the host.
\item A variable-sized data unit that is packetized by the HNI.
\item A fixed-sized data unit that is packetized by the host.
\item A fixed-sized data unit that is packetized by the HNI.
\end{enumerate}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Data Copying}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Memory space accessing - a user space and a kernel space
\item Data Path - Programmed I/O, DMA, burst transfer by memory
controller
\item Classification:   
 \begin{enumerate}
 \item 0-copy from user space on main memory to network.
 \item 1-copy from user space of main memory to network buffer memory,
 then to network. 
 \item 1-copy from user space of main memory to kernel space of main
 memory.
 \item 2-copy from user space to kernel space of main memory then to
 network buffer memory.
\end{enumerate}
\end{itemize}
\end{slide}

\begin{slide}
{\bf 0-copy from user space on main memory to network}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item The host processor informs data address and length to the
network protocol processor. 
\item The network protocol processor initiates DMA controller to
transfer data from a user space of main memory to network.
\end{itemize}
\vfill
\centerline{\psfig{figure=figures/UF.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf 1-copy from user space of main memory to network buffer memory,
 then to network}
\rule[0.1in]{8in}{0.02in}
After data is copied to network buffer memory, HNI provides
some other protocol processing such as CRC and composing of header
fields. 
\vfill
\centerline{\psfig{figure=figures/UNF.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf 1-copy from user space of main memory to kernel space of main
memory} 
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item To process protocol, data is copied to kernel space.
\item Good security and protection of data between users.
\end{itemize}
\vfill
\centerline{\psfig{figure=figures/UKF.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf 2-copy from user space to kernel space of main memory then to
network buffer memory} 
\rule[0.1in]{8in}{0.02in}
Transport protocol processing on kernel space except CRC
checking which is supported on host-network interface.
\vfill
\centerline{\psfig{figure=figures/UKNF.ps}} 
\vfill
\end{slide}

\begin{slide}
{\bf Flow Control}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item The flow of offered-data load just enough to achieve a
throughput that is very close to that of the resources' capacity 
\item  Receiver flow control schemes (RFC):
\begin{enumerate}
\item A receiving window by acknowledgements and sequence numbers 
\item Software-based for counting of the number of received packets
\item Hardware-based for counting of the number of received packets
\item Hardware-based measurement of the inter-packet arrival time
\item Accepting/discarding packets based on buffer availability
\end{enumerate}

\item State-reporting schemes (SR):
\begin{enumerate}
\item Window-based acknowledgements
\item The current inter-packet arrival time or burst size of packets
\item Start/stop control signal
\end{enumerate}

\item Transmitter flow control (TFC):
\begin{enumerate}
\item Sending packets based on current window size
\item Sending packets based on the current acceptable transmission rate
\item Sending packets based on start/stop control signal
\end{enumerate}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Error Handling}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item Error detection, and correction when the network is not
reliable.  
\item  Error-detection functions (D):
\begin{enumerate}
\item Cyclic Redundancy Check (CRC)
 \begin{itemize}
 \item Type: CRC-8, CRC-10, CRC-12, CRC-16, CRC-32, CRC-CCITT.
 \item Domain: A control part, A data part, or A control $+$ data
 part. 
 \end{itemize}
\item Length indicator of data.
\item Sequence number.
\item Multiplexing identifier (MID).
\end{enumerate}

\item Error-correction functions (C):
\begin{enumerate}
\item Forward Error Correction (FEC).
\item Backward Error Correction/Automatic Repeat Request (ARQ).
\item FEC $+$ ARQ.
\end{enumerate}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Routing/Switching}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item When an application process sets up a connection to another
\item Address generating (or address resolution) function
\item Source address, destination address(es) and intermediate-node
addresses if needed. 
\item  At least, port numbers, host numbers, network numbers, and
frame numbers in TCP/IP suites
\item Classification:
\begin{enumerate}
\item Circuit switching
\item Source routing/packet switching
\item Internode routing/packet switching
\item Virtual circuit switching (statistical switching)
\end{enumerate}
\end{itemize}
\end{slide}

\begin{slide}
{\bf Illustrative Example: AURORA}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item AURORA - An experimental wide area network testbed 
\item Operation at near giga-bit per second bandwidths 
\item HNI converts data between the network format (ATM cells) and
a format useful to the host (transport level message - TPDU)
\item OSIRIS for TURBOchannel bus on DECstation 5000 
\item ORBIT for MICROchannel bus on the IBM RS/6000 
\end{itemize}
\end{slide}

\begin{slide}
{\bf Continue...}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=figures/L1-DMA-uP.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Continue...}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=figures/L2-AURORA.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Simple HNI Design}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item ATM network with AAL-5 
\item A cost-effective system: minimal hardware support
\item Easy adjustments to the changes of environment
\item low speed network and multiple protocol support environment
\end{itemize}
\end{slide}

\begin{slide}
{\bf Design Requirements}
\rule[0.1in]{8in}{0.02in}

In architectural context:
\begin{itemize}
\item Conection component - Comparative bandwidth to that of the
system bus
\item Fast processing of the cell header error checking
\end{itemize}

In protocol context:
\begin{itemize}
\item Routing - only the source's and destination's addresses
\item Data copying - main memory to network FIFO
\item Error handling - in ATM network, CRC checking, sequence
numbering, MID, data length indicator and FEC + ARQ
\item Flow control - simple implementation. 
\item Packetization - fixed sized payload
\end{itemize}
\end{slide}

\begin{slide}
{\bf Taxonomy-based Design Approach}
\rule[0.1in]{8in}{0.02in}
\begin{itemize}
\item In the architectural context, 
\begin{itemize} 
\item Connection between main memory and network FIFO by direct memory
access: DMA for $M_H - FIFO$.  
\end{itemize}

\item In protocol implementation context, 
\begin{itemize}
\item Virtual circuit switching.
\item Zero data copying between user space of main memory and network FIFO.
\item CRC-8 by hardware for header error check, CRC-10 by software for
data error check, sequence number, MID, and length indicator of data.
\item Window-based and rate-based flow control
\end{itemize}
\end{itemize}

\end{slide}

\begin{slide}
{\bf Diagram for Archtiectural context of simple HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter4/figures/L1-simpleHNI.ps}}
\vfill
\end{slide}

\begin{slide}
{\bf Diagram for protocol context of simple HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter4/figures/L2-simpleHNI.ps}}
\vfill
\end{slide}


\begin{slide}
{\bf Transmitting Performance of simple HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
To send 1 payload data (384 bits), \\
6 slow loads and 6 slow stores through the 64-bit PCI system bus.
\vfill
For the header information, \\
1 slow store (since less than 1 fast load for the header information
and CRC field), 5 arithmatic and 1 branch instructions.

\vfill
\begin{eqnarray*}
Throughput & = & \frac{48\ byte/cell \times 8\ bit/byte}{(6 L^s_{\mu
 p} + 7 S^s_{\mu p} + 6 computation) T_{\mu p}} \\    
 & = & \mbox{} \frac{384}{(22 + 22 + 6) (30.3 \times 10^{-9})} \\   
 & = &  \mbox{}  248.50 Mbps
\end{eqnarray*}
\vfill
\end{slide}

\begin{slide}
{\bf Segmentation Performance of simple HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter5/figures/segthruput-simple.ps,width=4.5in,height=4.5in}}
\vfill
\end{slide}

\begin{slide}
{\bf Receiving Performance of simple HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
Reassembly by a lightly loaded host for an ATM cell:
6 loads (7-2-2-2-7-2) by 64 bit DMA B/W; 3 (7-2-2) stores by 128 bit
memory B/W.  

\begin{eqnarray*}
Throughput & = & \frac{48 Bytes}{( 6 L^s_{\mu p} +  3 S^s_{\mu p} +
12\ computation) T_{up}} \\
   & = & \mbox{} \frac{384}{(22 + 11 + 12) 30.3 \times 10^{-9} } \\
   & = & 281.63 \ Mbps
\end{eqnarray*}

In heavy loaded host: additional 3 slow loads from main memory.

\begin{eqnarray*}
Throughput & = & \frac{48 Bytes}{( 6 L^s_{\mu p} + 3 L^s_{\mu p} + 3
S^s_{\mu p} + 12\ computation) T_{up}} \\
   & = & \mbox{} \frac{384}{(22 + 11 + 11 + 12) 30.3 \times 10^{-9} } \\
   & = & 226.31 \ Mbps
\end{eqnarray*}

\vfill
\end{slide}

\begin{slide}
{\bf Reassembly Performance of simple HNI}
\rule[0.1in]{8in}{0.02in}
\vfill
\centerline{\psfig{figure=../book/chapter5/figures/reasmthruput-simple.ps,width=4.5in,height=4.5in}}
\vfill
\end{slide}

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\end{document}
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