Processing-In-Memory (PIM) Architectures

Acknowledgements

Memory & CPU Bandwidth Gap

Key Points

This Talk: A Better Way!

Observations on This Talk

HPCC & TeraFlops

Petaflop Chain of Events

Results from Pasadena ‘94

PetaFlops Applications

Pasadena Architectures

Bodega Bay: Primary Memory

Bodega Bay: Secondary Memory

Bodega Bay: Aggregate I/O

Cost Considerations: Processors

Cost Considerations: Memory

The “Hidden Costs” of Modern Systems

The Overlooked Bandwidth

Modern “Alternative” RAMs

Processing In Memory (PIM):

PIM: Optimizing the System

Market Demand for Dense Processing

Current PIM Chips

Key Problem: Memory Density

Vendors with Known DRAM PIM Capability

EXECUBE: The First High Density PIM

Execube Processing Node

Tiling of Execube Processing Nodes

Lessons Learned from EXECUBE

New “Strawman” PIM

“Strawman” Chip Floorplan

Strawman Chip Interfaces

Strawman PIM Chip with I/O Macros

Strawman Properties

Strawman PIM “Memory Card”

Choosing the Processing Macro

Performance Per Transistor

SIA-Based PIM Chip Projections

Silicon Area for a Teraflop

Parallelism

Petaflop PIM System Size

Power Projections (Logic)

Power Per Sq. Cm

3D Stacking

Potential PIM Cube

Potential PIM Cube

Further Work: Hardware

Further Work:Algorithm Development

Further Work: Software Development

Current ND PIM Work In Progress

Conclusion