Basic HTML version of Foils prepared 24 August 98

Foil 24 Shared Memory MIMD Multiprocessor

From Master Foilset for CPS615 Introduction -- Material from Culler and Koelbel Computational Science for Simulations -- Fall Semester 1998. by Geoffrey C. Fox, Nancy McCracken
Processors access shared memory via bus
Low latency, high bandwidth
Bus contention limits scalability
Search for scalability introduces locality
  • Cache (a form of local memory)
  • Multistage architectures (some memory closer)
Examples: Cray T90, SGI Power Challenge, Sun

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