Basic HTML version of Foils prepared August 24 1996

Foil 2 Conventional Microprocessor Unit Performance Path

From Some Numerical Memory and MicroProcessor Projections for PetaFlops JNAC (PetaFlops) Presentation -- August 28,1996. by Peter Kogge Notre Dame
1 Assumes:
2 * 100% efficient utilization
3 * SIA Growth in Clock Rate
4 * Growth in instruction issue parallelism
5 In 2004 technology (for 2007 machine)
6 160,000 such processors gives 1 PF peak.
7 Problem: each requires caches, memory, I/O!
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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