Find this at http://www.npac.syr.edu/users/gcf/PPTKoggeJNAC3/

Some Numerical Memory and MicroProcessor Projections for PetaFlops

This was part of a set of PetaFlop (JNAC) Presentations to group of Federal Program Managers

JNAC = Joint National Advanced Computing Initiative

This uses Moore's Law Projections of Technology for Logic and Memory

and uses Bodega Bay Application Analysis to cost memory for a "realistic" machine

Table of Contents for Some Numerical Memory and MicroProcessor Projections for PetaFlops

001 Technology Projections
002 Conventional Microprocessor Unit Performance Path
003 Primary Memory Chip Cost
004 Notes on Primary Memory $
005 Bodega Bay Petaflops Applications Characteristics
006 Achieving 1 PF vs Bodega Bay Applications

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu