Basic HTML version of Foils prepared June 1996
Foil 23 Current PIM Chips
From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
| 1 |
Storage
|
| 2 |
0.5 MB
|
| 3 |
0.5 MB
|
| 4 |
0.05 MB
|
| 5 |
0.128 MB
|
| 6 |
Chip
|
| 7 |
EXECUBE
|
| 8 |
AD SHARC
|
| 9 |
TI MVP
|
| 10 |
MIT MAP
|
| 11 |
Terasys PIM
|
| 12 |
First
|
| 13 |
Silicon
|
| 14 |
1993
|
| 15 |
1994
|
| 16 |
1994
|
| 17 |
1996
|
| 18 |
1993
|
| 19 |
Peak
|
| 20 |
50 Mips
|
| 21 |
120 Mflops
|
| 22 |
2000 Mops
|
| 23 |
800 Mflops
|
| 24 |
625 M bit
|
| 25 |
ops
|
| 26 |
0.016 MB
|
| 27 |
MB/
|
| 28 |
Perf.
|
| 29 |
0.01
|
| 30 |
MB/Mip
|
| 31 |
0.005
|
| 32 |
MB/MF
|
| 33 |
0.000025
|
| 34 |
MB/Mop
|
| 35 |
0.00016
|
| 36 |
MB/MF
|
| 37 |
0.000026
|
| 38 |
MB/bit op
|
| 39 |
Organization
|
| 40 |
16 bit
|
| 41 |
SIMD/MIMD CMOS
|
| 42 |
Single CPU and
|
| 43 |
Memory
|
| 44 |
1 CPU, 4 DSP's
|
| 45 |
4 Superscalar
|
| 46 |
CPU's
|
| 47 |
1024
|
| 48 |
16-bit ALU's
|
Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu
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