Basic HTML version of Foils prepared June 1996

Foil 34 Strawman Properties

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Huge bandwidths available to processing logic
  • "Free" 4 line cache at the sense amps
  • Minimal addressing delays => minimal latency
2 Tremendous internode bandwidths
  • "Built in" local shared memory
3 Huge bandwidths available at chip periphery
4 2D tiling prevents wires "over memory"
5 Opportunity for "mix and match"
  • Memory macros
  • Processing logic
  • External I/O protocols
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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