Basic HTML version of Foils prepared June 1996

Foil 44 3D Stacking

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
Goal: create 3D cubes of silicon
Process:
  • "Thin" die to 7 mils or smaller
  • "Glue" together
  • Plate wires on sides
Stacks of 70 or more have been demonstrated
Ideal for PIMs
  • Same chip type throughout
  • Most side wires: common or chip-chip
  • "Contact explosion" avoidable
Problems Today: >2 side wiring, Power

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Apr 11 1999