Basic HTML version of Foils prepared 20 February 00

Foil 51 Importance of Memory Structure in High Performance Architectures

From Introduction to Computational Science CPS615 Computational Science Class -- Spring Semester 2000. by Geoffrey C. Fox


1 Actually memory bandwidth is an essential problem in any computer as doing more computations per second requires accessing more memory cells per second!
  • Harder for sequential than parallel computers
2 Key limit is that memory gets slower as it gets larger and one tries to keep information as near to CPU as possible (in necessarily small size storage)
3 This Data locality is unifying concept of caches (sequential) and parallel computer multiple memory accesses
4 Problem seen in extreme case for Superconducting CPU's which can be 100X current CPU's but seem to need to use conventional memory

in Table To:


© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Thu Mar 16 2000