Implementations for the parallel block-diagonal-bordered sparse
Gauss-Seidel method have been developed during this
research. Pseudo-code representations of each parallel algorithm
section are presented separately in figures
through
. In particular, each of these figures
correspond to the following figure numbers:
Figure: The Iterative Framework for the Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm
Figure: Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm --- Diagonal Blocks
Figure: Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm --- Update --- Low-Latency Communications Paradigm
Figure: Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm --- Update --- Buffered Communications Paradigm
Figure: Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm --- Last Diagonal Block --- Low-Latency Communications Paradigm
Figure: Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm --- Last Diagonal Block --- Buffered Communications Paradigm
Figure: Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm --- Convergence Check --- Low-Latency Communications Paradigm
Figure: Parallel Block-Diagonal-Bordered Sparse Gauss-Seidel Algorithm --- Convergence Check --- Buffered Communications Paradigm