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Conclusions

 

We have shown that the superb computation-to-communication ratio available on the CM-5 using low-latency active messages will probably not be equaled in future SPP architectures where processor performance increases significantly. Performance of our parallel Gauss-Seidel algorithm is latency dependent, due to the large number of small messages. Meanwhile, performance of our parallel direct algorithm is bandwidth dependent, due to the limited number of moderate sized messages.

We have shown that while the parallel sparse block-diagonal-bordered direct solvers may port to future architectures with equal or better performance, the parallel sparse block-diagonal-bordered Gauss-Seidel solvers may not. While future architectures will have greater bandwidth than the Thinking Machines CM-5, they will not have a comparable reduction for communications latency. Any algorithmic performance gains possible with the parallel Gauss-Seidel algorithm would not be realized on future architectures that do not have the computation-to-communication ratio available on the CM-5.



David P. Koester
Sun Oct 22 17:27:14 EDT 1995