Basic HTML version of Foils prepared August 24 1996

Foil 2 Conventional Microprocessor Unit Performance Path

From Some Numerical Memory and MicroProcessor Projections for PetaFlops JNAC (PetaFlops) Presentation -- August 28,1996. by Peter Kogge Notre Dame
Assumes:
* 100% efficient utilization
* SIA Growth in Clock Rate
* Growth in instruction issue parallelism
In 2004 technology (for 2007 machine)
160,000 such processors gives 1 PF peak.
Problem: each requires caches, memory, I/O!

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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