Basic HTML version of Foils prepared June 1996

Foil 4 Key Points

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Today's High Performance Systems
  • Expensive, Multiple Chips and Chip types
  • Based on conventional wisdom
    • Use fastest possible uP and densest DRAM
    • Coupled with fast but costly hierarchy
  • This is Not Optimal!
    • Separate chips waste inherent bandwidth
      • Forcing more chips
    • Poor use of silicon AND chip-chip contacts
    • Poor technology insertion
      • New uP ==> New system
    • Poor scaling
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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