Basic HTML version of Foils prepared June 1996

Foil 21 PIM: Optimizing the System

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Ample bandwidth changes design philosophy
  • Do: Optimize silicon to solve problems efficiently
    • Minimize total system silicon
    • Minimize total system power
    • Minimize design complexity
  • Don't: Force designers into
    • Single highest performance CPU solution
    • With complex bandwidth recovery logic
  • Natural outgrowth of PIM Philosophy
    • Simple, single part type
    • Scalable solutions
    • Inherently parallel
    • VERY "DENSE" PROCESSING
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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