Basic HTML version of Foils prepared June 1996

Foil 32 Strawman Chip Interfaces

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Combined Memory Bus/Chip Control
  • "Look like memory" to a host
  • Memory mapped SIMD Instruction Broadcast
  • Memory mapped I/O (esp. System) Control
2 Chip to Chip Links to support scalable MPPs
3 External system links:
  • To other chip clusters
  • To high speed I/O
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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