Basic HTML version of Foils prepared June 1996

Foil 44 3D Stacking

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Goal: create 3D cubes of silicon
2 Process:
  • "Thin" die to 7 mils or smaller
  • "Glue" together
  • Plate wires on sides
3 Stacks of 70 or more have been demonstrated
4 Ideal for PIMs
  • Same chip type throughout
  • Most side wires: common or chip-chip
  • "Contact explosion" avoidable
5 Problems Today: >2 side wiring, Power
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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