Basic HTML version of Foils prepared June 1996

Foil 47 Further Work: Hardware

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Core "conventional" CPU selection:
  • More accurate area & performance estimates
  • Power projections
2 Optimal PIM ISA & Organization
  • Memory structures program visible
  • Embedded PIM MPP support
3 Optimized PIM memory macro
  • Scalable size
  • Processing "at the sense amps"
4 Selection of I/O Protocols
5 Integrated CAD support
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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