From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. byPeter Kogge Notre Dame
HPCC Program: Conceived in late 1980's
Key Goal: Tera(fl)op by turn of century
Spurred new architectures, esp. MPPs
1 TF in sight! Eg. Recent Intel Award
Major impediment: 1 TF = BIG MACHINE!
Final component: Embedded HPCC
NASA's REE Program recently initiated
We have declared Success!
Next Goal: Petaflops!
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