Basic HTML version of Foils prepared June 1996

Foil 15 Cost Considerations: Processors

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
Today:
  • 100 MF uP => 1,000,000 CPUs for 100 TF
  • At 10 Support Chips/CPU => 10,000,000 Chips
Future:
  • 10X Clock
  • 4X In Issues/Cycle
  • Still 250,000 Chips
NOT COUNTING MEMORY!
"Glows in the Dark"

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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