Basic HTML version of Foils prepared June 1996

Foil 29 Lessons Learned from EXECUBE

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
Absolute Need: DENSEST POSSIBLE Memory
Single Part Type => True Scalable Systems
Bandwidth "Next Door" => Simpler CPU
Integrated, Fast I/O => Simpler Apps
Mixed SIMD/MIMD => Simple Parallelization
Next Time:
  • Memory macro organization is Key
  • Add more CPU visibility into Memory Macro
  • "Generalize" SIMD Bus
  • Support for Virtual Shared Memory
  • I/O for Chip-Chip & System-System
  • Floating point

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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