Basic HTML version of Foils prepared Sept 19, 1996

Foil 17 III. Key drivers: Technological Limitations

From PetaFlop(JNAC) Overview Presentations -- Results of Studies and Next Steps Sep 19,96 NSTC Committee Presentation -- Sept 19,1996. by Paul Smith DoE
Semiconductor component technology
  • feature size, other issues will finally put us in a regime in which Moore's law no longer holds
Architecture
  • levels of parallelism must be used
  • memory hierarchy due to increased processor speeds
System software
  • latency management
  • efficient handling of
    • millions of concurrent threads
    • thousands of I/O devices

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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