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Next: B: Superconducting Design Up: I: Petaflops Architectures Previous: I: Petaflops Architectures

A: Conventional Distributed Shared Memory Silicon Architecture

  1. Clock Speed, 1 GHz
  2. Four eight-way parallel complex C.P.U.'s per processor chip, giving a peak 32 Gigaflops
    performance per chip
  3. 8,000 processing chips giving over 0.25 Petaflops peak performance
  4. 32,000 2 Gigabytes memory chips, giving 64 Terabytes of memory

Geoffrey Fox, Northeast Parallel Architectures Center at Syracuse University, gcf@npac.syr.edu