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Next: II. Programming Environments for Up: I: Petaflops Architectures Previous: B: Superconducting Design

C: Processor in Memory PIM

  1. Maybe this would need to be fair to use ``previous generation'' half-Gigabyte chips.
  2. One divides memory real estate into processor and memory using ``simple'' 250,000 transistor C.P.U.'s. Each memory chip, if divided equally in area between C.P.U. and memory could have 250 1 Gigaflops C.P.U.'s each with one Megabyte of memory.
  3. 32,000 modified memory chips leads to 8 Terabytes of memory, and 8 Petaflops performance.

Superconducting technologies machines are characterized by dramatic disparity between C.P.U. and memory performance. The PIM architecture has good memory access for problems where the data can be laid out geometrically in a fashion (probably two dimensional) that matches the machine. The PIM architecture only has modest memory per CPU (which can be increased by using less than 50% of the silicon real estate for C.P.U.) which suggests it may need to be integrated with conventional (class A) nodes to handle sophisticated operating system functionality. This makes PIM machines like ``attached processors'' but with very flexible C.P.U.'s.



Geoffrey Fox, Northeast Parallel Architectures Center at Syracuse University, gcf@npac.syr.edu