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LOCAL foilset Some Numerical Memory and MicroProcessor Projections for PetaFlops

Given by Peter Kogge Notre Dame at JNAC (PetaFlops) Presentation on August 28,1996. Foils prepared August 24 1996
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This was part of a set of PetaFlop (JNAC) Presentations to group of Federal Program Managers
JNAC = Joint National Advanced Computing Initiative
This uses Moore's Law Projections of Technology for Logic and Memory
and uses Bodega Bay Application Analysis to cost memory for a "realistic" machine

Table of Contents for Some Numerical Memory and MicroProcessor Projections for PetaFlops

1 Separate IMAGE * Separate HTML Technology Projections
2 Separate IMAGE * Separate HTML Conventional Microprocessor Unit Performance Path
3 Separate IMAGE * Separate HTML Primary Memory Chip Cost
4 Separate IMAGE * Separate HTML Notes on Primary Memory $
5 Separate IMAGE * Separate HTML Bodega Bay Petaflops Applications Characteristics
6 Separate IMAGE * Separate HTML Achieving 1 PF vs Bodega Bay Applications
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Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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