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Master Set A of Overview Material on Parallel Computing for CPS615
Given by
Geoffrey C. Fox
at CPS615 Basic Simulation Track for Computational Science on
Fall Semester 95
.
Foils prepared
29 August 1995
Secs 30
Technology Driving Forces for HPCC
Overview of What and Why is Computational Science
Needs to be expanded with further remarks on Information track and degree/certificate requirements
Elementary Discussion of Parallel Computing in the "real-world"
Hadrian Wall example
Sequential Computer Architecture
Table of Contents for Master Set A of Overview Material on Parallel Computing for CPS615
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1
CPS615 -- Base Course for the Simulation Track of Computational Science
Fall Semester 1995
Foilsets A
2
Contents of Foilsets A of CPS615 Computational Science
3
The Technology
Driving Forces for HPCC
4
Effect of Feature Size on Performance
5
Growing Logic Chip Density
6
Trends in Feature and Die Size as a Function of Time
7
Supercomputer Memory Sizes and trends in RAM Density
8
Comparison of Trends in RAM Density and CPU Performance Increases
9
National Roadmap for Semiconductor Technology --1992
10
CMOS Technology and Parallel Processor Chip Projections
11
What and Why is Computational Science ?
12
Parallelism Implies Major Changes which have significant educational Implications
13
Program in Computational Science
Implemented within current academic framework
14
Program in Information Age Computational Science Implemented Within Current Academic Program
15
Elementary Discussion of
Parallel Computing
16
Single nCUBE2 CPU Chip
17
64 Node nCUBE Board
18
CM-5 in NPAC Machine Room
19
Basic METHODOLOGY of Parallel Computing
20
Concurrent Computation as a Mapping Problem -I
21
Concurrent Computation as a Mapping Problem - II
22
Concurrent Computation as a Mapping Problem - III
23
Finite Element Mesh From Nastran
(mesh only shown in upper half)
24
A Simple Equal Area Decomposition
25
Decomposition After Annealing
(one particularly good but nonoptimal decomposition)
26
Parallel Processing and Society
27
Concurrent Construction of a Wall
Using N = 8 Bricklayers
Decomposition by Vertical Sections
28
Quantitative Speed-Up Analysis for Construction of Hadrian's Wall
29
Amdahl's law for Real World Parallel Processing
30
Pipelining --Another Parallel Processing Strategy for Hadrian's Wall
31
Hadrian's Wall Illustrates that the Topology of Processor Must Include Topology of Problem
32
General Speed Up Analysis
33
Comparison of The Complete Problem to the subproblems formed in domain decomposition
34
Hadrian's Wall Illustrating an
Irregular but Homogeneous Problem
35
Some Problems are Inhomogeneous Illustrated by:
An Inhomogeneous Hadrian Wall with Decoration
36
Global and Local Parallelism Illustrated by Hadrian's Wall
37
Parallel I/O Illustrated by
Concurrent Brick Delivery for Hadrian's Wall
Bandwidth of Trucks and Roads
Matches that of Masons
38
Nature's Concurrent Computers
39
Comparison of Concurrent Processing in Society and Computing
40
Sequential Computer Architecture
41
Sequential Computer Architecture
42
Instruction Flow in A Simple Machine Pipeline
43
Examples of Superpipelined (a) and superscaler (b) machine pipelines
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on Tue Oct 7 1997