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Master Set A of Overview Material on Parallel Computing for CPS615

Technology Driving Forces for HPCC

Overview of What and Why is Computational Science Needs to be expanded with further remarks on Information track and degree/certificate requirements

Elementary Discussion of Parallel Computing in the "real-world" Hadrian Wall example

Sequential Computer Architecture

Table of Contents for Master Set A of Overview Material on Parallel Computing for CPS615

001 CPS615 -- Base Course for the Simulation Track of Computational 
    Science
    Fall Semester 1995
    Foilsets A
002 Contents of Foilsets A of CPS615 Computational Science
003 The Technology 
    Driving Forces for HPCC
004 Effect of Feature Size on Performance
005 Growing Logic Chip Density
006 Trends in Feature and Die Size as a Function of Time
007 Supercomputer Memory Sizes and trends in RAM Density
008 Comparison of Trends in RAM Density and CPU Performance Increases
009 National Roadmap for Semiconductor Technology --1992
010 CMOS Technology and Parallel Processor Chip Projections
011 What and Why is Computational Science ?
012 Parallelism Implies Major Changes which have significant 
    educational Implications
013 Program in Computational Science
    Implemented within current academic framework
014 Program in Information Age Computational Science Implemented 
    Within Current Academic Program
015 Elementary Discussion of
    Parallel Computing
016 Single nCUBE2 CPU Chip
017 64 Node nCUBE Board
018 CM-5 in NPAC Machine Room
019 Basic METHODOLOGY of Parallel Computing
020 Concurrent Computation as a Mapping Problem -I
021 Concurrent Computation as a Mapping Problem - II
022 Concurrent Computation as a Mapping Problem - III
023 Finite Element Mesh From Nastran
    (mesh only shown in upper half)
024 A Simple Equal Area Decomposition
025 Decomposition After Annealing
    (one particularly good but nonoptimal decomposition)
026 Parallel Processing and Society
027 Concurrent Construction of a Wall
    Using N = 8 Bricklayers
    Decomposition by Vertical Sections
028 Quantitative Speed-Up Analysis for Construction of Hadrian's Wall
029 Amdahl's law for Real World Parallel Processing
030 Pipelining --Another Parallel Processing Strategy for Hadrian's 
    Wall
031 Hadrian's Wall Illustrates that the Topology of Processor Must 
    Include Topology of Problem
032 General Speed Up Analysis
033 Comparison of The Complete Problem to the subproblems formed in 
    domain decomposition
034 Hadrian's Wall Illustrating an
    Irregular but Homogeneous Problem
035 Some Problems are Inhomogeneous Illustrated by:
    An Inhomogeneous Hadrian Wall with Decoration
036 Global and Local Parallelism Illustrated by Hadrian's Wall
037 Parallel I/O Illustrated by
    Concurrent Brick Delivery for Hadrian's Wall
    Bandwidth of Trucks and Roads
    Matches that of Masons
038 Nature's Concurrent Computers
039 Comparison of Concurrent Processing in Society and Computing
040 Sequential Computer Architecture 
041 Sequential Computer Architecture
042 Instruction Flow in A Simple Machine  Pipeline
043 Examples of Superpipelined (a) and superscaler (b) machine 
    pipelines