Basic HTML version of Foils prepared 19 September 1997

Foil 4 64 Node nCUBE Board

From Master Set of Foils for 1997 Session of CPS615 CPS615 Basic Simulation Track for Computational Science -- Fall Semester 97. by Geoffrey C. Fox

Secs 34
1 Each node is CPU and 6 memory chips -- CPU Chip integrates communication channels with floating, integer and logical CPU functions

in Table To:


© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Feb 22 1998