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CPS615 - Overview of Computer Architectures
Given by Geoffrey C. Fox at CPS615 Basic Simulation Track for Computational Science on Fall Semester 97. Foils prepared 19 September 1997
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We describe the simple nature of parallel machines like the nCUBE2
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Technologies include conventional, superconducting and Quantum systems but the former dominates
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Sequential architectures are dominated by memory (cache) issues
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Vector, SIMD MIMD are classic architectures
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There is a growing interest in distributed metacomputers
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Special purpose machines are typically not so successful
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The details of networks is not as important as it used to be!
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This mixed presentation uses parts of the following base foilsets which can also
be looked at on their own!
CPS615Master97 Master Set of Foils for 1997 Session of
CPS615
CPS615-95A Master Set A of Overview Material on
Parallel Computing for CPS615 Foils
CPS615Master96 Master Set of Foils for 1996 Session of
CPS615
SmithPetaOverview2 PetaFlop(JNAC) Overview Presentations --
Results of Studies and Next Steps Sep
19,96
GeneralFoils97 Variety of Foils Used Starting January 97
GeneralResFoils96 Miscellaneous Presentation Material used in
1996
CornellHPCCOverview96MasterMaster Foils for A Short Overview of HPCC
-- From GigaFlops to PetaFlops and From
Tightly Coupled MPP's to the World Wide
Web
KoggePimTalk Processing-In-Memory (PIM) Architectures
for Very High Performance MPP Computing
CPS615-95B Master Set B of Overview Material on
Parallel Computing for CPS615 Foils
DynamicWebPagesgivenbyURL Title and Abstract of FakeFoilset
A Brief Discussion of Computer Architectures
- Enough to motivate Introductory Technologies
- Start with ncube2 Pictures
CPS615Master97 024 001 Introduction to Computer
Architectures CPS615 Fall
Semester 97
CPS615Master97 025 002 Abstract of CPS615 Architecture
Discussion
CPS615-95A 016 003 Single nCUBE2 CPU Chip
CPS615-95A 017 004 64 Node nCUBE Board
Technologies of Relevance
CPS615Master96 012 005 Technologies for High Performance
Computers
CPS615Master96 013 006 Architectures for High Performance
Computers - I
CPS615Master96 014 007 Architectures for High Performance
Computers - II
CPS615Master96 015 008 There is no Best Machine!
CPS615Master96 016 009 Quantum Computing - I
CPS615Master96 017 010 Quantum Computing - II
CPS615Master96 018 011 Quantum Computing - III
CPS615Master96 019 012 Superconducting Technology -- Past
CPS615Master96 020 013 Superconducting Technology --
Present
CPS615Master96 021 014 Superconducting Technology --
Problems
Summer 97 Technology Updates!
CPS615Master97 011 015 Ames Summer 97 Workshop on Device
Technology -- Moore's Law - I
CPS615Master97 012 016 Ames Summer 97 Workshop on Device
Technology -- Moore's Law - II
CPS615Master97 013 017 Ames Summer 97 Workshop on Device
Technology -- Alternate
Technologies I
CPS615Master97 014 018 Ames Summer 97 Workshop on Device
Technology -- Alternate
Technologies II
CPS615Master97 015 019 Ames Summer 97 Workshop on Device
Technology -- New Logic Concepts
CPS615Master97 016 020 Ames Summer 97 Workshop on Device
Technology -- RSFQ
CPS615Master97 017 021 Ames Summer 97 Workshop on Device
Technology -- QCA -I
CPS615Master97 018 022 Ames Summer 97 Workshop on Device
Technology -- QCA -II
Architecture Overview and Sequential
CPS615Master97 021 023 Sequential Memory Structure
CPS615Master96 022 024 Architecture Classes of High
Performance Computers
CPS615Master96 023 025 von Neuman Architecture in a
Nutshell
CPS615Master96 024 026 Illustration of Importance of
Cache
Vector Architecture
CPS615Master96 025 027 Vector Supercomputers in a
Nutshell - I
CPS615Master96 026 028 Vector Supercomputing in a picture
CPS615Master96 027 029 Vector Supercomputers in a
Nutshell - II
General Pipelining Issues
CPS615Master97 026 030 What is a Pipeline -- Cafeteria
Analogy?
CPS615-95A 042 031 Instruction Flow in A Simple
Machine Pipeline
CPS615Master97 027 032 Example of MIPS R4000 Floating
Point
CPS615Master97 028 033 MIPS R4000 Floating Point Stages
General Parallel Architectures
CPS615Master96 028 034 Flynn's Classification of HPC
Systems
Parallel Memory Structure
CPS615Master96 029 035 Parallel Computer Architecture
Memory Structure
CPS615Master96 030 036 Comparison of Memory Access
Strategies
CPS615Master96 031 037 Types of Parallel Memory
Architectures -- Physical
Characteristics
CPS615Master96 032 038 Diagrams of Shared and Distributed
Memories
Parallel Control Structure
CPS615Master96 033 039 Parallel Computer Architecture
Control Structure
MIMD Architectures
CPS615Master96 034 040 Some Major Hardware Architectures
- MIMD
CPS615Master96 035 041 MIMD Distributed Memory
Architecture
CPS615Master97 029 042 Cache Coherent or Not?
CPS615Master97 030 043 Choices in Cache Coherence
SIMD Architectures
CPS615Master96 036 044 Some Major Hardware Architectures
- SIMD
CPS615Master96 037 045 SIMD (Single Instruction Multiple
Data) Architecture
Metacomputers
CPS615Master96 038 046 Some Major Hardware Architectures
- Mixed
CPS615Master96 039 047 Some MetaComputer Systems
Special Purpose Devices
CPS615Master96 040 048 Comments on Special Purpose
Devices
CPS615Master96 041 049 The GRAPE N-Body Machine
CPS615Master96 042 050 Why isn't GRAPE a Perfect
Solution?
Granularity
CPS615Master96 043 051 Granularity of Parallel Components
- I
CPS615Master96 044 052 Granularity of Parallel Components
- II
Application Motivation for PetaFlops
SmithPetaOverview2 015 053 III. Key drivers: The Need for
PetaFLOPS Computing
GeneralFoils97 007 054 10 Possible PetaFlop Applications
GeneralResFoils96 031 055 Petaflop Performance for Flow in
Porous Media?
GeneralResFoils96 032 056 Target Flow in Porous Media
Problem (Glimm - Petaflop
Workshop)
GeneralResFoils96 033 057 NASA's Projection of Memory and
Computational Requirements upto
Petaflops for Aerospace
Applications
The 3 classes of PetaFlop Designs
CornellHPCCOverview96Master 005 058 Supercomputer Architectures in
Years 2005-2010 -- I
CornellHPCCOverview96Master 006 059 Supercomputer Architectures in
Years 2005-2010 -- II
CornellHPCCOverview96Master 007 060 Supercomputer Architectures in
Years 2005-2010 -- III
KoggePimTalk 037 061 Performance Per Transistor
CornellHPCCOverview96Master 008 062 Comparison of Supercomputer
Architectures
The Processor in Memory Design
KoggePimTalk 023 063 Current PIM Chips
KoggePimTalk 030 064 New "Strawman" PIM
Processing Node Macro
KoggePimTalk 031 065 "Strawman" Chip
Floorplan
KoggePimTalk 038 066 SIA-Based PIM Chip Projections
Parallel Computer Networks
CPS615Master96 045 067 Classes of Communication Networks
CPS615Master96 046 068 Switch and Bus based Architectures
CPS615Master96 047 069 Examples of Interconnection
Topologies
CPS615Master96 048 070 Useful Concepts in Communication
Systems
Network and Computer Performance
CPS615-95B 021 071 Latency and Bandwidth of a Network
CPS615-95B 022 072 Transfer Time in Microseconds for
both Shared Memory Operations and
Explicit Message Passing
CPS615-95B 023 073 Latency/Bandwidth Space for 0-byte
message(Latency) and 1 MB
message(bandwidth).
CPS615Master96 049 074 Communication Performance of Some
MPP's
CPS615Master96 050 075 Implication of Hardware
Performance
DynamicWebPagesgivenbyURL 003 076 Netlib Benchweb Benchmarks
DynamicWebPagesgivenbyURL 004 077 Linpack Benchmarks
DynamicWebPagesgivenbyURL 005 078 Java Linpack Benchmarks
List of Foils Used as they occur
CPS615Master97 Master Set of Foils for 1997 Session of
CPS615
24 25 11 12 13 14 15 16 17 18 21 26 27 28 29 30
CPS615-95A Master Set A of Overview Material on
Parallel Computing for CPS615 Foils
16 17 42
CPS615Master96 Master Set of Foils for 1996 Session of
CPS615
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SmithPetaOverview2 PetaFlop(JNAC) Overview Presentations --
Results of Studies and Next Steps Sep
19,96
15
GeneralFoils97 Variety of Foils Used Starting January 97
7
GeneralResFoils96 Miscellaneous Presentation Material used in
1996
31 32 33
CornellHPCCOverview96MasterMaster Foils for A Short Overview of HPCC
-- From GigaFlops to PetaFlops and From
Tightly Coupled MPP's to the World Wide
Web
5 6 7 8
KoggePimTalk Processing-In-Memory (PIM) Architectures
for Very High Performance MPP Computing
37 23 30 31 38
CPS615-95B Master Set B of Overview Material on
Parallel Computing for CPS615 Foils
21 22 23
DynamicWebPagesgivenbyURL Title and Abstract of FakeFoilset
3 4 5
Sorted List of Foils Used
CPS615Master97 Master Set of Foils for 1997 Session of
CPS615
11 12 13 14 15 16 17 18 21 24 25 26 27 28 29 30
CPS615-95A Master Set A of Overview Material on
Parallel Computing for CPS615 Foils
16 17 42
CPS615Master96 Master Set of Foils for 1996 Session of
CPS615
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SmithPetaOverview2 PetaFlop(JNAC) Overview Presentations --
Results of Studies and Next Steps Sep
19,96
15
GeneralFoils97 Variety of Foils Used Starting January 97
7
GeneralResFoils96 Miscellaneous Presentation Material used in
1996
31 32 33
CornellHPCCOverview96MasterMaster Foils for A Short Overview of HPCC
-- From GigaFlops to PetaFlops and From
Tightly Coupled MPP's to the World Wide
Web
5 6 7 8
KoggePimTalk Processing-In-Memory (PIM) Architectures
for Very High Performance MPP Computing
23 30 31 37 38
CPS615-95B Master Set B of Overview Material on
Parallel Computing for CPS615 Foils
21 22 23
DynamicWebPagesgivenbyURL Title and Abstract of FakeFoilset
3 4 5
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