Basic HTML version of Foils prepared 23 August 1998

Foil 23 Parallel Computer Memory Structure

From CPS615-Introduction-Course,Driving Technology and HPCC Current Status and Futures CPS615 Basic Simulation Track for Computational Science -- Fall Semester 98. by Geoffrey C. Fox, (Some Culler, Koelbel material)
For both parallel and sequential computers, cost is accessing remote memories with some form of "communication"
Data locality addresses in both cases
Differences are quantitative size of effect and what is done by user and what automatically
Processor
Cache
L2 Cache
L3 Cache
Main
Memory
Processor
Cache
L2 Cache
Processor
Cache
L2 Cache
Board Level Interconnection Networks
....
....
System Level Interconnection Network
L3 Cache
Main
Memory
L3 Cache
Main
Memory
Slow
Very Slow

© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sat Aug 29 1998