Full Index for Scripted foilset 
| This starts with a discussion of Parallel Computing using analogies from nature |
| It uses foils and material from CSEP chapter on Computer Architecture to discuss how and why to build a parallel computer including synchronization memory structure and network issues |
| SIMD and MIMD Architectures with a brief comparison of workstation networks with closely coupled systems |
| A look to the future is based on results from Petaflops workshop |
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1
CPS615 -- Base Course for the Simulation Track of Computational Science
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Abstract of Lecture Stream 2 of CPS615 
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Elementary Discussion of
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Single nCUBE2 CPU Chip
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64 Node nCUBE Board
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CM-5 in NPAC Machine Room
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Basic METHODOLOGY of Parallel Computing
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Concurrent Computation as a Mapping Problem -I
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Concurrent Computation as a Mapping Problem - II
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Concurrent Computation as a Mapping Problem - III
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Finite Element Mesh From Nastran
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A Simple Equal Area Decomposition
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Decomposition After Annealing
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Parallel Processing and Society
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Concurrent Construction of a Wall
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Quantitative Speed-Up Analysis for Construction of Hadrian's Wall
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Amdahl's law for Real World Parallel Processing
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Pipelining --Another Parallel Processing Strategy for Hadrian's Wall
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Hadrian's Wall Illustrates that the Topology of Processor Must Include Topology of Problem
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General Speed Up Analysis
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Comparison of The Complete Problem to the subproblems formed in domain decomposition
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Hadrian's Wall Illustrating an
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Some Problems are Inhomogeneous Illustrated by:
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Global and Local Parallelism Illustrated by Hadrian's Wall
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Parallel I/O Illustrated by
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Nature's Concurrent Computers
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Comparison of Concurrent Processing in Society and Computing
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Computational Science CPS615
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Abstract of CPS615 Foilsets B 1995
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Overview of
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3 Major Basic Hardware Architectures
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Examples of the Three Current Concurrent Supercomputer Architectures
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Parallel Computer Architecture Issues
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General Types of Synchronization
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Granularity of Parallel Components
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Types of Parallel Memory Architectures
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Types of Parallel Memory Architectures -- Physical Characteristics
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Diagrams of Shared and Distributed Memories
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Survey of Issues in Communication Networks
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Glossary of Useful Concepts in Communication Systems
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Switch and Bus based Architectures
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Classes of Communication Network include ...
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Point to Point Networks (Store and Forward) -- I
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Examples of Interconnection Topologies
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Degree and Diameter of Ring and Mesh(Torus) Architectures
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Degree and Diameter of Hypercube and Tree Architectures
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Rules for Making Hypercube Network Topologies
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Mapping of Hypercubes into Three Dimensional Meshes
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Mapping of Hypercubes into One Dimensional Systems
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The One dimensional Mapping can be thought of as for one dimensional problem solving or one dimensional layout of chips forming hypercube
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Hypercube Versus Mesh Topologies
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Point to Point Networks (Store and Forward) -- II
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Latency and Bandwidth of a Network
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Transfer Time in Microseconds for both Shared Memory Operations and Explicit Message Passing
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Latency/Bandwidth Space for 0-byte message(Latency) and 1 MB message(bandwidth).
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Switches versus Processor Networks
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Circuit Switched Networks
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Let's Return to General Parallel Architectures in more detail
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Overview of Computer Architecture Issues
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Some Global Computer Architecture Issues
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Two General Real World Architectural Issues
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MIMD Distributed Memory Architecture
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Some MIMD Architecture Issues
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SIMD (Single Instruction Multiple Data) Architecture
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SIMD Architecture Issues
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Shared Memory Architecture
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Shared versus Distributed Memory
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The General Structure of a full sized CRAY C-90
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The General Structure of a NEC SX-3
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Comparison of MIMD and SIMD Parallelism seen on Classic Vector Supercomputers
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What will happen in the year 2015 with .05 micron feature size and Petaflop Supercomputers using CMOS
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CMOS Technology and Parallel Processor Chip Projections
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Processor Chip Requirements for a Petaflop Machine Using 0.05 Micron Technology
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Three Designs for a Year 2015 Petaflops machine with 0.05 micron technology
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The Global Shared Memory Category I Petaflop Architecture
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Category II Petaflop Architecture -- Network of microprocessors
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Category III Petaflop Design -- Processor in Memory (PIM)
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Necessary Latency to Support Three Categories
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Chip Density Projections to year 2013
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DRAM Chip count for Construction of Petaflop computer in year 2013 using 64 Gbit memory parts
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Memory Chip Bandwidth in Gigabytes/sec
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Power and I/O Bandwidth (I/O Connections) per Chip throught the year 2013
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Clock Speed and I/O Speed in megabytes/sec per pin through year 2013 Full WebWisdom URL and this Foilset Search
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