Scripted HTML version of Foils prepared 18 Sept 1995

Foil 5 64 Node nCUBE Board

From Second set of lectures on CPS615 Parallel Computing Overview CPS615 Basic Simulation Track for Computational Science -- Fall Semester 95. by Geoffrey C. Fox *
Secs 34
Each node is CPU and 6 memory chips -- CPU Chip integrates communication channels with floating, integer and logical CPU functions

© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Fri Aug 15 1997