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GLOBAL foilset HPCC Current Status: Hardware MPP

Given by Geoffrey Fox at Trip to China on July 12-28,96. Foils prepared July 6 1996
More Detail! * Foil Index from this file * See also color IMAGE

We describe basic technology driver -- the CMOS Juggernaut -- and some new approaches that could be important 10-20 years from now
We describe from elementary point of view the basics of parallel(MPP) architectures
We discuss current situation for tightly coupled systems -- convergence to distributed shared memory
We discuss clusters of PC's/workstations -- MetaComputing


This mixed presentation uses parts of the following base foilsets which can also be looked at on their own!
General Collection of Research Foils -- July--December 1996
Master Set A of Overview Material on Parallel Computing for CPS615 Foils
Master Set B of Overview Material on Parallel Computing for CPS615 Foils
Collection of GIF Images for General NPAC Projects April96-
MetaComputing -- the Informal Supercomputer

Table of Contents for HPCC Current Status: Hardware MPP


1 Separate IMAGE * Separate HTML Status of "Classic" HPCC -- June1996
Summary of MPP Hardware
2 Separate IMAGE * Separate HTML Abstract of HPCC Hardware Status 1996
3 Separate IMAGE * Separate HTML Some HPCC Hardware Architectures and Their Status - I

Start new Section:Technology Driving Forces
4 Separate IMAGE * Separate HTML The Technology
Driving Forces for HPCC
5 Separate IMAGE * Separate HTML Effect of Feature Size on Performance
6 Separate IMAGE * Separate HTML Growing Logic Chip Density
7 Separate IMAGE * Separate HTML Trends in Feature and Die Size as a Function of Time
8 Separate IMAGE * Separate HTML Supercomputer Memory Sizes and trends in RAM Density
9 Separate IMAGE * Separate HTML Comparison of Trends in RAM Density and CPU Performance Increases
10 Separate IMAGE * Separate HTML National Roadmap for Semiconductor Technology --1992
11 Separate IMAGE * Separate HTML CMOS Technology and Parallel Processor Chip Projections

Elementary Architecture Discussion

12 Separate IMAGE * Separate HTML Parallel Computer Architecture Issues
13 Separate IMAGE * Separate HTML Granularity of Parallel Components
14 Separate IMAGE * Separate HTML Types of Parallel Memory Architectures
-- Logical Structure
15 Separate IMAGE * Separate HTML Types of Parallel Memory Architectures -- Physical Characteristics
16 Separate IMAGE * Separate HTML Diagrams of Shared and Distributed Memories
17 Separate IMAGE * Separate HTML Classes of Communication Network include ...
18 Separate IMAGE * Separate HTML Examples of Interconnection Topologies
19 Separate IMAGE * Separate HTML Latency and Bandwidth of a Network
20 Separate IMAGE * Separate HTML Transfer Time in Microseconds for both Shared Memory Operations and Explicit Message Passing
21 Separate IMAGE * Separate HTML Latency/Bandwidth Space for 0-byte message(Latency) and 1 MB message(bandwidth).
22 Separate IMAGE * Separate HTML Some HPCC Hardware Architectures and Their Status - II
23 Separate IMAGE * Separate HTML Shared versus Distributed Memory

MetaComputing
24 Separate IMAGE * Separate HTML Gordon Bell's SNAP Architecture - I
25 Separate IMAGE * Separate HTML Gordon Bell's SNAP Architecture - II
26 Separate IMAGE * Separate HTML Gordon Bell's SNAP Architecture - III
27 Separate IMAGE * Separate HTML Mark Baker's Review of MetaComputing/Cluster Management Projects

Follow with some of Overview from Mark Baker's Talk at CRPC

28 Separate IMAGE * Separate HTML Alternative Supercomputing Resources
29 Separate IMAGE * Separate HTML Parallel/Distributed Computing - Communications Characteristics
30 Separate IMAGE * Separate HTML Some Comments about Parallel and Distributed Computing
31 Separate IMAGE * Separate HTML Communications Performance of Some Parallel and Distributed Systems
32 Separate IMAGE * Separate HTML Distributed Systems: Some Problems

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