HELP! * YELLOW=global GREY=local Global HTML version of Foils prepared July 6 1996

Foil 21 Performance Per Transistor

From HPCC Status -- TeraFlop to Web and Petaflops -- Success and Failure Trip to China -- July 12-28,96. by Geoffrey Fox * Critical Information in IMAGE
Performance data from uP vendors
Transistor count excludes on-chip caches
Performance normalized by clock rate
Conclusion: Simplest is best! (250K Transistor CPU)
Millions of Transistors (CPU)
Millions of Transistors (CPU)
Normalized SPECINTS
Normalized SPECFLTS
Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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