Separate HTML for GLOBAL Foil 8 Category III Petaflop Design -- Processor in Memory (PIM)

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Foil 8 Category III Petaflop Design -- Processor in Memory (PIM)

From Software and System Issues in use of Optical Interconnects in MPPs MPPOI 95 Conference -- 24 October 95. by Geoffrey C. Fox * Critical Information in IMAGE

See Chapter 6 of Petaflops Report -- July 94

This design is an extrapolation of systems such as the J machine(Dally), Execube (Loral) or Mosaic(Seitz). It features CPU and memory integrated on the chip (PIM).

Unlike such systems today, in the year 2015 such PIM designs have substantial memory per processor

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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