HTML version of Scripted Foils prepared April 27 97

Foil 6 Performance Per Transistor

From And the HPCN Future is: Petaflop Computers and Java and Web Technologies Aachen Parallel Computing Workshop, Pallas Presentation Germany -- April 21,23 97. by Geoffrey C. Fox *
1 Performance data from uP vendors
2 Transistor count excludes on-chip caches
3 Performance normalized by clock rate
4 Conclusion: Simplest is best! (250K Transistor CPU)
5 Millions of Transistors (CPU)
6 Millions of Transistors (CPU)
7 Normalized SPECINTS
8 Normalized SPECFLTS
Table Font Size

© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Aug 10 1997