Currently MPP's have COTS processors and specialized networks but this could reverse
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Pervasive ATM will indeed lead to COTS Networks BUT
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Current microprocessors are roughly near optimal in terms of megaflops per square meter of silicon BUT
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As (explicit) parallelism shunned by modern microprocessor, silicon is used for wasteful speculative execution with expectation that future systems will move to 8 way functional parallelism.
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Thus estimate that 250,000 transistors (excluding on chip cache) is optimal for performance per square mm of silicon
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Modern microprocessor is around ten times this size
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Again simplicity is optimal but this requires parallelism
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Contrary trend is that memory dominates use of silicon and so performance per square mm of silicon is often not relevant
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