All proposed hardware architectures have a complex memory hierarchy which should be abstracted with a software architecture
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Consisting of a mix of machine specific and generic levels with well defined ADI's or Abstract Device Interfaces
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Management of latency with concurent threads or otherwise critical
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This implies a layered software architecture reflected in all components
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Compiler Language and Runtime, Tools, Systems Software etc.
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The Software Architecture should be defined early on so that hardware and software respect it!
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JNAC Architecture Review Board will be responsible for interfaces and evaluating compliance with them
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Users and Compilers must be able to have full control of data movement and placement in all parts of petaflop system
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Size and Complex Memory Structure of PetaFlop machines represent major challenges in scaling existing Software Concepts
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