Basic HTML version of Foils prepared 17 November 1998

Foil 153 Performance Per Transistor

From Master Foilset for HPC Achitecture Overview CPS615 Basic Simulation Track for Computational Science -- Fall Semester 98. by Geoffrey C. Fox
1 Performance data from uP vendors
2 Transistor count excludes on-chip caches
3 Performance normalized by clock rate
4 Conclusion: Simplest is best! (250K Transistor CPU)
5 Millions of Transistors (CPU)
6 Millions of Transistors (CPU)
7 Normalized SPECINTS
8 Normalized SPECFLTS
in Table To:

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