Basic HTML version of Foils prepared
17 November 1998
Foil 68 ncube1 Chip -- integrated CPU and communication channels
From
Master Foilset for HPC Achitecture Overview CPS615 Basic Simulation Track for Computational Science --
Fall Semester 98
.
by
Geoffrey C. Fox
This and related transputer design were very iunnovative but failed as could not exploit commodity microprocessor design economies
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Basic HTML version of Foils prepared 17 November 1998
