Parallelism in processing
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multiple operations per cycle reduces CPI
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soon thread level parallelism
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Cache to give locality in data access
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avoids latency and reduces CPI
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also improves processor utilization
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Both need (transistor) resources, so tradeoff
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ILP (Instruction Loop Parallelism) drove performance gains of sequential microprocessors
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ILP Success was not expected by aficionado's of parallel computing and this "delayed" relevance of scaling "outer-loop" parallelism as user's just purchased faster "sequential machines"
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CPI = Clock Cycles per Instruction
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