Basic HTML version of Foils prepared Sept 19, 1996

Foil 29 V. A National program concept: Research Projects - Technology

From PetaFlop(JNAC) Overview Presentations -- Results of Studies and Next Steps Sep 19,96 NSTC Committee Presentation -- Sept 19,1996. by Paul Smith DoE
Chip Interface:
  • Fabrication Technology
  • Laser & CMOS chip integration
Optical Networks:
  • Pbps bandwidths
  • 1000 ports
Superconducting Memories:
  • 100 billion accesses/sec.
Holographic Memories

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Apr 11 1999